Lamb Labs — Daxos teardown

The pitch

Convert an existing language model into a diffusion architecture that decodes tokens in parallel, get 2× faster inference on GPUs you already own, then build custom silicon that reaches 20,000+ tokens per second at 63× higher intelligence per watt. Four stages: diffusion post-training and an FPGA prototype are marked shipped, their own board is in bring-up, and the ASIC is what they call the endgame.

Harmonic has them at $500,000 in a single round dated 24 June 2026, sole investor Y Combinator, headcount 2. That lands in the cheapest funding band, which is worth a full point of bonus under our scoring. Strip that bonus out and this is a 2.0.

What is genuinely real

More than the empty-looking homepage suggests, and worth saying plainly before the rest. Niki Kotecha has three substantive commits on a public branch named lamb/main, forking Cornell's QTIP quantization work and patching it for Qwen3 validation runs. They reference a private internal compression repo. That is real hands-on engineering from nine days ago. There is a complete, professional PCB layout with their logo on the silkscreen. There is a demo screenshot whose arithmetic is internally consistent: 31.9 tokens per second against 62.5, which is the 2× they claim. Something does run on a Xilinx dev board; they have recorded it twice.

For two people six weeks past incorporation, that is fast work. It is also the entire inventory.

The three findings that decide it

1. Stage 02 "shipped" may be someone else's project. Thomas Lanning forked adamgallas/llama-fpga on 18 July 2026 — a 179-star open-source FPGA accelerator whose README names the Kria KV260 as a supported platform and runs LLaMA2-7B in 4-bit. He pushed zero commits to it. His "only 6W to run a 7B param model" demo went up the next day, 19 July, on the same board at the same model size. This is circumstantial, not proof, and it is the first question to put to them.

2. The hardware claim moved three times in three weeks and never once carried a speed. 7B at 6W on LinkedIn (19 July), 8B under 10W on the website, 27B at sub-7W on Hacker News (5 August). Power and parameter count every time; tokens per second never. On that Hacker News post Thomas described his own result as "unbelievably slow."

3. The software advantage inverts exactly where the revenue is. Their 2× is a batch-of-one measurement. In batched serving, which is how inference is actually sold, the published literature has autoregressive models running 13.7× faster than diffusion at batch 32, with the diffusion model running out of memory at batch 16 and above. Bidirectional attention cannot reuse a KV cache; that is architectural, not a tuning problem. Their "no loss in quality" claim needs splitting. Cheap block-diffusion conversion really does hold up — SDAR converts on 50B tokens and comes out level or better (MMLU 82.2 to 82.8, HumanEval 84.8 to 87.2). But block diffusion keeps causal attention across blocks, which is exactly why it keeps the KV cache and only decodes 2 to 3.5 tokens per forward pass. The full-bidirectional conversion that would deliver the parallel decoding they describe is the one that costs 65B tokens and drops TriviaQA from 45.4 to 18.5, PIQA from 78.3 to 63.3, HellaSwag from 74.9 to 58.7. They cannot have the cheap version and the parallel version at once.

Founders

	Niki Kotecha	Thomas Lanning
Training	PhD Process Systems Engineering, Imperial. MEng Chemical Engineering, Cambridge.	MSc Mathematical & Theoretical Physics, Oxford. Top of class, Edinburgh.
Work history	~8 months of AI research roles (Ergodic, U Toronto)	None in engineering. CV shows manual labour jobs in Australia, Oct 2024 to May 2025.
Semiconductors	None	None. Self-taught in code; lists PCB design as a hobby he is exploring.
Publications	PhD-track	None

Neither has designed a chip. There is no chip-engineering hire, and no job posting for one, at a company whose stated endgame is a tape-out. That is the cleanest available read on what stage this actually is.

One item needs raising directly rather than assumed either way. Thomas's YC bio credits him with rediscovering the Higgs boson using machine learning and CERN data. The repository behind that claim never mentions the Higgs boson, and the data is output from a detector simulation he wrote himself rather than CERN open data. That is the CEO's headline credential on a public fundraising page. Ask him to walk through it.

Both halves of the pitch are already owned

	Raised	People	Position
Taalas	$338M	25	Identical hardware thesis — model weights hardwired into silicon. Founded 26 months before Lamb. 676× the capital.
Inception	$56M	40	Identical software thesis. Mercury 2 shipping on AWS Bedrock and Azure Foundry. Stefano Ermon and Stanford behind it.
Etched	$1.84B	481	What reaching first silicon actually costs. Four years to customer validation.
Cerebras	$10.3B	966	Holds the speed record: about 2,000 tok/s single-stream. Nothing independently measured exceeds that, from anyone.
Lamb Labs	$500K	2	—

The 20,000 tok/s headline resolves two ways, and both are fatal

This number is the company. It sits at the end of a four-stage roadmap and justifies a tape-out. It is also, to within a quarter of a percent, the aggregate throughput of one stock Nvidia B200 on an 8B model, shipping today.

MLPerf Inference v6.0, Llama 3.1 8B	Per accelerator, offline	Per accelerator, server
Nvidia B200	20,050 tok/s	16,409 tok/s
Nvidia B300	20,843 tok/s	18,508 tok/s
Lamb Labs Stage 04 target	20,000+

Read as aggregate, the endgame ASIC equals a GPU you can buy this afternoon. That is not a weak moat, it is a description of the incumbent.

Read as single-stream, it is roughly ten times the fastest wafer-scale machine ever built. Cerebras spent $10.3B to reach about 2,000. The arithmetic is closed, not merely hard: 20,000 tokens per second on a 7B model at FP8 means fetching 7 GB twenty thousand times, or 140 TB/s of memory bandwidth. A B200 has 8 TB/s. That is 17.5 GPUs in perfect tensor parallel with zero interconnect cost, inside a 50 microsecond per-token budget where one NVLink all-reduce already costs 1 to 3.

And their answer to that bandwidth problem — put the weights on-chip — does not fit. An 8B model at INT4 needs roughly 1,165 mm² of SRAM. The lithography reticle limit is 858 mm². The weights do not go on one die, which is the premise the whole architecture rests on.

One calibration note for anything they quote later: Groq markets 1,000 tok/s per user and independent measurement puts it at 455. Apply the same discount.

The deeper problem: they want to bake a decoding scheme into silicon

Set the capital aside for a moment. The technical thesis has a documented hole, and it is the reason this is riskier than an ordinary hardware bet.

Diffusion decoding buys single-stream latency. It gives that back under batch load — the throughput gains "vanish beyond saturation" (Optimus, arXiv 2605.24832), and a June 2026 survey of the field concludes that "parallel generation alone does not guarantee practical speedups." A separate study found current parallel decoding methods "consistently underperform the single-token decoding baseline."

It also costs measurable intelligence. Google's own numbers put Gemini Diffusion at 69.1% MMLU against 79.0% for Gemini 2.0 Flash-Lite. The cleanest illustration is Inception's own shipping product: Mercury 2 scores 21 on the intelligence index at 786 tok/s, while autoregressive Gemini 3.5 Flash-Lite scores 36 at 367 tok/s and costs less. Twice the speed, well under half the capability.

Now commit that to fixed silicon. An ASIC cannot be revised for four years. Lamb proposes to hard-wire a decoding scheme whose advantage is measured at batch 1, degrades exactly as utilisation rises, and currently trades away ten to fifteen points of capability — into a part they cannot change once it tapes out. That is the specific risk to put to the founders, and it is sharper than any argument about their bank balance.

The category

Across 30 funded AI-chip startups, only 23% ever returned more than the money put in. Restrict that to the post-2022 capital regime and it is 6.7%. Untether went bankrupt and AMD took the engineering team explicitly without the technology. Blaize raised $403M and trades at 92 cents. Rain AI — the YC-backed AI chip precedent, the closest thing to a direct comparable — is down to 11 people. Groq, the best independent inference-ASIC company there was, ended up inside Nvidia via a $20B license after $2.5B and nine years.

The arithmetic underneath: Nvidia resets performance per watt every 12 months, and Rubin ships this quarter with a 2.5× jump. An ASIC design-to-silicon cycle is 18 to 24 months minimum. You tape out against a target that has already moved twice.

For

Cheapest funding band. $500K entry, full +1.0 bonus.
Real, timestamped engineering output from a two-person team.
A professional custom PCB design exists.
YC S26, Tyler Bosmeny as group partner.
Inference energy is a genuinely large problem.

Against

Zero semiconductor experience across both founders.
No chip hire, and no posting for one.
Core software advantage inverts under batched serving.
Headline numbers are Stage 04 targets, not measurements.
The 2× sits in the lower middle of a published range running 1.2× to 12.9×. Not differentiated.
Inception — the authors who founded this field — ship diffusion LLMs on stock GPUs. If it needed custom silicon they would be building it.
London entity, so ineligible for SBIR under 13 CFR 121.702 — the usual non-dilutive path for defense-adjacent silicon is closed.
No customers, LOIs, design partners, revenue, papers or third-party benchmarks.
Capital need is 100–1000× what we write; a pre-seed position dilutes to nothing over 7–13 rounds.
Founders are describing different companies — sub-1W edge versus 20,000 tok/s datacenter.
Open-source release promised for the week of 10 Aug; the Hugging Face org is still empty.

Questions if we take the call

1	Is the KV260 accelerator your own RTL, or adamgallas/llama-fpga? You forked it the day before the demo.
2	What is the tokens per second on the FPGA? Three power figures are public and no speed figure is.
3	MLPerf v6.0 shows one B200 at 20,050 tok/s offline on Llama 3.1 8B. Your Stage 04 target is 20,000+. Is that single-stream or aggregate — and if aggregate, what does the ASIC buy that a B200 does not?
3b	An 8B model at INT4 needs ~1,165 mm² of SRAM against an 858 mm² reticle. How do the weights go on-chip?
3c	Where does 63× come from — synthesis, an analytical model, or the objective function of your own RL search reported back as a result?
4	Your 2× is batch-1. What happens at batch 8, 16, 32?
5	Your YC bio credits you with rediscovering the Higgs boson using CERN data. The repo shows a self-built simulation and never mentions it. Walk me through that.
6	Are you selling sub-1W edge parts or 20,000 tok/s datacenter parts? Your launch posts say different things.

3.0

Pass.

The work is real and the velocity is notable, but this is not fundable at our check size. Reaching silicon costs nine figures, and a pre-seed position in a company that will raise seven to thirteen more rounds is worth approximately nothing by the time anything tapes out. The headline throughput number is either one commodity GPU or something no hardware can do, and the on-chip-weights answer to it exceeds the reticle limit. Meanwhile the one asset that does not need a fab — the diffusion converter — is held more credibly by a company with 100× the capital that is already shipping through two hyperscaler marketplaces, and the published evidence says the technique loses to plain autoregressive decoding at production batch sizes.

There is a version of this we could underwrite, and it is not the one being pitched: diffusion-converted models for power-constrained, batch-of-one edge inference, sold as software plus an FPGA reference board, with the ASIC explicitly deferred. That plays to the one advantage they actually hold — at batch 1 you cannot amortise weight reads across users, and diffusion is the only known way to raise arithmetic intensity without them — and it needs no fab. For context on the road they have chosen instead: $50M is the honest NRE floor for a simple accelerator ASIC (Alchip’s CEO), rising past $100M with chiplets, while a full 7nm design program runs about $298M and 5nm about $542M (IBS). Only 14% of ASIC projects reach working first silicon, and nobody has done it in under four years.

Worth watching one thing. If the converter ships and an independent party benchmarks 2× at batch 8 or higher on standard hardware with no quality regression, the software half of this becomes a different conversation. The silicon half does not.